Logik is an open source FPGA toolchain that completely automates transforming RTL to bits, consisting of synthesis, positioning, routing, bitstream generation, and analysis. Users go into style sources, restraints, and assemble choices through an easy SiliconCompiler Python API. When setup is total, automatic collection can be started with a single line run command.
Logik supports the majority of the functions you would anticipate in a business exclusive FPGA tool chain.
Function Status Design languages Verilog, SystemVerilog, VHDL ALU synthesis Supported RAM synthesis Supported Timing restraints (SDC) Supported Pin Constraints (PCF) Supported Bitstream generation Supported IP management Supported Remote collection Supported Multi-clock styles In development FPGA gadgets ZA
Beginning
The Logik job is offered through PyPi and can be set up utilizing pip. If you wish to run in your area on your device, you will require to set up all of the pre-requisites or release the Logik Docker image.
python -m pip set up– upgrade logik
The copying highlight some vital Logik functions. For total paperwork of all alternatives offered, see the SiliconCompiler task.
from siliconcompiler import Chip from logik.targets import logik_target def hello_adder(): # Create collection things chip = Chip(‘adder') # Specify style sources chip.input(‘adder.v') # Specify pin restrictions chip.input(‘adder.pcf') # Compiler choices chip.set(‘choice', ‘peaceful', True) chip.set(‘alternative', ‘remote', True) # Select target fpga chip.set(‘fpga', ‘partname', ‘logik_demo') # Load target settings chip.load _ target(logik_target) # Run compiler chip.run() # Display compiler outcomes chip.summary() if __ name __ == “__ primary __”: hello_adder()
This code can be kept up./ adder.py -remote in the examples/adder directory site, leading to an FPGA bitstream at build/adder/job0/ convert_bitstream/ 0/outputs/adder. bin.
To evaluate out the created bitstream, you can submit it to an imitated FPGA gadget running in the Zero ASIC Digital Twin Platform.
More Examples
- UMI “Hello World”
- UMI FIR Filter
- EBRICK demonstration
Paperwork
- Logik Documentation
- SiliconCompiler Documentation
Setup
Logik is offered as wheel bundles on PyPI for macOS, Windows and Linux platforms. For a Python 3.8-3.12 environment, simply utilize pip to set up.
python -m pip set up– upgrade logik
Running natively on your regional device will need setting up a variety of requirements:
- Silicon Compiler: Hardware compiler structure
- Yosys: Logic synthesis
- VPR: FPGA location and path
- GHDL: VHDL parser
- Surelog: SystemVerilog parser
- FASM: FPGA assembly parser and generator
Automated Ubuntu based set up scripts are consisted of for benefit within the SiliconCompiler task. In-depth directions for setting up all tools can be discovered in the SiliconCompiler Installation Guide.
Running Docker
A Docker image is offered users who want to prevent the setup of the pre-requisite tools. The following command begins a brand-new container from that image and maps the regional directory site sc_work to the course/ sc_work in the container.
docker run -it -v “$ / sc_work:/ sc_work” ghcr.io/ siliconcompiler/sc _ runner: newest
MIT
We utilize GitHub Issues for tracking demands and bugs.
